Johnson Counter

A Johnson counter is a modified ring counter in which the output from the last flip flop is inverted and fed back as an input to the first. It is also called as Inverse Feedback Counter or Twisted Ring Counter.

Ring counters are used in hardware logic design, as found for example within ASIC and FPGA ICs, to create complicated finite state machines (FSMs). An FSM is defined by a list of its states, its initial state, and the conditions for each transition between states. Traffic lights with programmed sequences, and combination locks are FSM examples.

The Johnson counter circulates a stream of ones followed by zeroes around the ring. For example, in a four-register counter, with initial register values of 0000, the repeating pattern is: 0000, 1000. 1100, 1110, 1111, 0111, 0011, 0001, 0000….

Ring counters offer some advantages over binary counters; these require an adder circuit, which is substantially more complex. Additionally, the worst-case propagation delay on an adder circuit is proportional to the number of bits in the code (due to the carry propagation). The ring counter propagation delay is constant regardless of the number of bits in the code. The complex combinational logic of an adder can create timing errors which may cause erratic hardware performance.

The disadvantage of ring counters is that they are lower density codes. A binary counter can represent 2^N states, where N is the number of bits in the code, whereas a Johnson counter can represent only 2N states.