Application benefits of using 4th Generation SiC MOSFETs

ROHM has released the 4th generation of SiC MOSFETs. It has achieved a 40% reduction in on-resistance and a 50% reduction in switching loss compared to the 3rd generation. This article describes an experimental test using a step-down DC-DC converter with 500V input voltage and 7kW power, a simulated running test using an EV traction inverter with 800V input and 100kW, and an experimental test using a Totem-pole PFC circuit.

However, as the world is currently strengthening its efforts to protect the global environment, simply improving comfort will not be enough to gain acceptance in the global market. In the future, in addition to improving convenience, it will become increasingly important to reduce energy loss and use it effectively. The key point to focus on is power conversion. In all the above-mentioned applications, power is supplied from the power grid, batteries, solar power generation systems, etc., and converted to the optimal voltage for effective use. To reduce energy loss and increase power conversion efficiency, SiC power semiconductors are currently attracting attention for their ability to operate at high frequency, high voltage and high current density with low energy loss. ROHM has already commercialized SiC power semiconductors, which are used in a variety of applications.

Figure 1. Application examples.

ROHM has released the 4th generation of SiC MOSFETs. By further evolving the trench gate structure established in the 3rd Generation SiC MOSFETs already in mass production, ROHM has reduced on-resistance by approximately 40% and switching loss by approximately 50% due to high-speed switching characteristics compared to the 3rd generation. This evolution is shown in the trend of normalized on-resistance (Ron-A: on-resistance per unit area) shown in Figure 2.

Figure 2. Trend graph of normalized on-resistance

In contrast to the 3rd Generation SiC MOSFETs, the 4th generation offer improved switching speed, which contributes significantly to lower switching losses. Figure 3(a) shows the block diagram of the buck converter and Figure 3(b) shows the general switching waveforms of the converter.

Figure 3. Block diagram of the buck converter (Figure 3a) and the general switching waveforms of the converter (Figure 3b).

As shown in Figure 3(b), power device losses in a converter consist of switching losses, conduction losses, body diode losses, recovery losses, and Coss losses. (Coss loss is omitted from the figure because it is small.)

As for switching loss, it is generally described in the datasheet as energy per Eon and Eoff pulse, which is a useful for loss estimation in the initial design stage. In detailed design, it is necessary to strictly determine the power dissipation at high voltage input and high frequency. The gate driving circuitry has a large impact in the device losses, so optimizing the gate drive design is necessary to take advantage of the high-speed switching characteristics of SiC devices.

Experimental Verification of DC-DC Converter

In order to confirm previous analysis, the 4th Generation SiC MOSFETs was incorporated into a step-down DC-DC converter with the following specifications and verified it experimentally with an evaluation board (table 1).

Figure 4 shows (a) the DC-DC converter circuit and (b) the evaluation board for the 4th Generation SiC MOSFETs used in the half-bridge section with built-in decoupling capacitor. The inductor L, output capacitor Co, and input bulk capacitor are external.

Table 1. Specifications of DC-DC Converters and SiC Device

Figure 4. DC-DC converter block diagram for test and 4th generation SiC MOSFET EVK.

Figure 5 displays the VGS, VDS, and ID waveforms at 50 kHz during turn-on and turn-off. The turn-on waveform is enlarged on the left. From the waveform observation, we can see that the turn-on rise time Trise is about 20ns, which is very fast. Figure 6 shows the measurement results of efficiency and power dissipation of this DC-DC converter as well as the efficiency and loss of the DC-DC converter. At light loads (around 1kW), the low switching loss, which is a characteristic of the 4th generation SiC MOSFET, is presented.

Figure 5. Observed switching waveforms (500Vin, 250Vo/20A(5kW), 50kHz)

Figure 6. Measured efficiency and losses (500Vin, 250Vo/7kW)

EV Application

There are various types of EVs, such as BEVs, HEVs, PHEVs, and series HEVs, with different power architectures for different applications. Among them, the power architecture of BEVs with 400V or 800V battery voltage supporting bi-directional and fast charging has been attracting attention recently.

Figure 7 illustrates a block diagram of the BEV power architecture as an example: the OBC (On-Board Charger) is a hot topic topology with bi-directional Totem-pole PFC and bi-directional CLLC (Symmetric LLC), assuming V2G (Vehicle To Grid). From the output of this OBC, power is supplied to the auxiliary DC-DC converter, the battery, the boost converter to the inverter and the motor traction inverter.

Figure 7. An example of BEV power architecture

Simulated driving test with traction inverter

As the integration of mechanical and electrical components (motors, reduction gears, and inverters) continues to progress, the importance of reducing losses to achieve high voltage, high output, compact, and lightweight inverters is increasing. This is because it directly affects the cost performance of EVs.

As shown in Figure 8, the traction inverter converts the DC power provided by the battery into 3-phase AC power to drive the motor in the powertrain. The three-phase AC waveform is set by a signal wave (reference sine wave) with a frequency synchronized with the motor speed, and a triangular wave (modulation wave) with a carrier frequency that determines the switching frequency. The voltage supplied to the motor is determined by changing the levels of the 3-phase AC and triangular waves when generating the PWM signal.

Figure 8. Inverter circuit configuration and drive signal

Motor test bench environment

Table 2 shows the main specifications of the SiC devices installed in the motor test bench and the DUT inverter. The DUT inverter consists of a 2-in-1 power module with a 4th generation SiC MOSFET bare chip.

Figure 8. Main specifications of motor test bench and test inverter

Figure 9 illustrates the control system block diagram. The test motor is driven from the DUT inverter through a 3-phase uvw power line. The test motor is connected to the load motor, and the load motor is controlled by the load torque according to the running resistance calculated from the vehicle parameters, which enables the simulated running experiment with the desired vehicle parameters.

Figure 9. Motor test bench / Control system block diagram

International Standard WLTC Mode Fuel Efficiency Test for Simulated Driving

The Worldwide Harmonized Light Duty Driving Test Cycle (WLTC) is a driving cycle specified in the Worldwide Harmonized Light Vehicles Test Procedure (WLTP). This cycle consists of Low, Middle, High, and Extra-High-speed phases. In Japan, test vehicles are driven in the driving cycle except for the Extra-High phase to measure exhaust emissions and fuel consumption.

Using the mentioned motor test bench, ROHM conducted a driving cost test using 4th Generation SiC MOSFETs and IGBTs in the inverter by inputting the conditions of a simulated WLTC driving cycle.

Figure 10 shows the results of the cost test assuming a C-segment class EV, demonstrating that replacing the conventional IGBTs with 4th generation SiC-MOSFETs can improve the cost in all speed phases of the WLTC driving cycle. The total power cost was improved by about 6% compared to the IGBTs, and by about 10% in the urban mode. For reference, Figure 11 shows a graph of the inverter efficiency map (based on the NT curve, with information on efficiency added). From this result, we can see that the efficiency in the high torque and low RPM range, which is frequently seen in urban driving, has been greatly improved.

Figure 10. Electricity cost test result

Figure 11. Inverter efficiency map in WLTC electric cost test

Evaluation of Totem-pole PFC

Totem-pole PFC is a topology that has attracted a great of attention in recent years as a PFC converter that can target high efficiency. In addition, V2G is being considered worldwide to stabilize the microgrid system and contribute to balancing supply and demand, and bidirectional operation has become important.

Figure 12 illustrates the circuit block diagram. The left leg (S1, S2) is for high frequency switching, and the right leg (S3, S4) is for commercial frequency (low frequency) rectification.

Figure 13 shows the operation diagram by state. During the positive half cycle of the commercial AC, the totem pole low side FET (S2) performs high frequency switching as a boost converter (Figure (a): period D). SiC MOSFETs have a very fast recovery time, and the effect of this power loss is small, so they are a good match for Totem-pole PFC power devices. Next, during the negative half cycle of the commercial AC, the totem-pole high-side FET (S1) acts as a boost converter, switching at high frequency (Figure (c): period D), while S2 acts as a rectifier (Figure (d): periods 1-D). S3 and S4 switch every half cycle of the commercial AC.

Figure 12. Totem-pole PFC block diagram

Figure 13. Operation diagram by state

To verify the contribution of the 4th Generation SiC MOSFETs to the loss reduction of the Totem-pole PFC, an experiment was conducted using the actual board. Table 3 shows the evaluation conditions of the PFC and the specifications of the SiC devices used. When the output voltage is 400V, a SiC MOSFET with 750V breakdown voltage is matched. In this case, SCT4045DR is used. As result, the measured efficiency is over 98% at 1.5kW half load and 97.6% at 3kW full load.

Figure 13. PFC evaluation condition

Summary

SiC power semiconductors are key power devices for increasing the convenience and power conversion efficiency in applications where high voltage and high current density are progressing, such as EVs, data centers, base stations, and smart grids. In the 4th Generation SiC MOSFET, the trade-off of the trench structure has been greatly improved, and the normalized on-resistance has been further reduced. The high-speed switching performance and low on-resistance of the 4th Generation SiC MOSFETs will greatly contribute to the improvement of power conversion efficiency.

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